1. Field of the Invention
This invention relates to an output circuit, specifically to an output circuit that includes at least two amplifiers.
2. Description of the Related Art
In general, ESD (Electrostatic Discharge) damage is caused in a MOS transistor when an excessive voltage due to an external noise is applied to it. Therefore, various protection measures are taken especially for a MOS transistor connected to an input or output terminal. In an output circuit shown in FIG. 8, an output of a first amplifier 1 and an output of a second amplifier 2 are connected to a common output pad (output terminal) P2. Each of the amplifiers 1 and 2 is driven by each of signals Φ1 and Φ2 from an internal circuit 3, respectively. The first amplifier 1 has a larger driving capacity than the second amplifier 2. Driving capacity of the combined amplifiers can be made variable by controlling the amplifiers so that either the first amplifier 1 or the second amplifier 2 is in operation, or both of the amplifiers 1 and 2 are in operation.
A high voltage side power supply terminal H1 of the first amplifier 1 is provided with a power supply voltage VDD from a power supply pad P1, while a low voltage side power supply terminal L1 of the first amplifier 1 is provided with a ground voltage VSS from a ground pad P3. Similarly, a high voltage side power supply terminal H2 of the second amplifier 2 is provided with the power supply voltage VDD from the power supply pad P1, while a low voltage side power supply terminal L2 of the second amplifier 2 is provided with the ground voltage VSS from the ground pad P3.
Each of the first amplifier 1 and the second amplifier 2 includes a CMOS inverter composed of a P-channel type MOS transistor and an N-channel type MOS transistor. The MOS transistors in the first amplifier 1 are designed to be larger in size (gate width GW) than the MOS transistors in the second amplifier 2, so that ON-resistance of the MOS transistors in the first amplifier 1 is lower than that in the second amplifier 2.
Also, in order to prevent ESD damage on the MOS transistors by an external noise applied to the power supply pad P1, the output pad P2 or the ground pad P3, a size of a contact hole of the MOS transistor connected directly to each of the pads, a distance between the contact hole and the gate, a gate length and a distance between a back gate and a source or a drain in both of the first and second amplifiers are designed to be of considerably larger sizes (ESD protection design rules) than minimum sizes according to design rules applied.
Further information related to the technologies described above is disclosed in Japanese Patent Application Publication No. H05-335493, for example.
However, designing both the first amplifier 1 and the second amplifier 2 to the ESD protection design rules results in increased sizes of the MOS transistors that constitute the amplifiers, and causes a problem of larger die size of the LSI (Large Scale Integration) in which the amplifiers are included.